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with Sem, In t, Busy
CY7C006 CY7C016
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Features
* True dual-ported memory cells which allow simultaneous reads of the same memory location * 16K x 8 organization (CY7C006) * 16K x 9 organization (CY7C016) * 0.65-micron CMOS for optimum speed/power * High-speed access: 15 ns * Low operating power: ICC = 140 mA (typ.) * Fully asynchronous operation * Automatic power-down * TTL compatible * Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device * Busy arbitration scheme provided * Semaphores included to permit software handshaking between ports * INT flag for port-to-port communication * Available in 68-pin PLCC (7C006), 64-pin (7C006) and 80-pin (7C016) TQFP * Pin compatible and functional equivalent to IDT7006/IDT7016 schemes are included on the CY7C006/016 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C006/016 can be utilized as a standalone 128-/144-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16-/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Enable (CE) pin or SEM pin. The CY7C006 and CY7C016 are available in 68-pin PLCC (CY7C006), 64-pin (CY7C006) TQFP and 80-pin (CY7C016) TQFP , .
R/W R CE R OE R
Functional Description
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8 and 16K x 9 dual-port static RAMs. Various arbitration
Logic Block Diagram
R/WL CE L OEL
(7C016) I/O 8L I/O7L I/O0L BUSYL
[1,2]
I/O CONTROL
I/O CONTROL
I/O 8R (7C016) I/O 7R I/O 0R BUSYR A 13R
[1,2]
A 13L A 0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER
A 0R
CE L OE L R/W L
INTERRUPT SEMAPHORE ARBITRATION
CER OER R/W R
SEM L INTL [2]
SEM R INTR[2] M/S
C006-1
Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 22, 1999
CY7C006 CY7C016
Pin Configurations
68-Pin PLCC Top View
NC(I/O8L[3]) OEL
SEML
R/WL
I/O1L
I/O0L
A13L
A12L
A11L A10L
CEL
VCC
A9L
A8L
A7L
68 67
66
65
64
63 62
61 60 59 58 57 56 55 54 53
9
8
7 6
5
4
3
2 1
A6L
NC
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 26
A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C006
52 51 50 49 48 47 46 45 44
NC(I/O8R[3] )
CER NC
SEMR
GND A12R
A13R
A11R A10R
A9R
A8R A7R
A6R
OER R/WR
I/O7R
A5R
C006-2
64-Pin TQFP Top View
SEML R/WL I/O1L I/O0L CEL A13L A12L A11L A10L OEL VCC A9L A8L A7L 52 A6L A5L 49
64
63
62 61
60
59
58
57
56 55
54
53
I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R
51 50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
48 47 46 45 44 43 42
A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R
CY7C006
41 40 39 38 37 36 35 34
17
18
19 20
21
22
23
24
25 26
27
28
29
30 31
32
16
33
R/WR
SEMR
CER A13R
GND
A12R
I/O6R
A11R A10R
A9R
A8R A7R
I/O7R
Note: 3. I/O for CY7C016 only.
OER
2
A6R A5R
C006-3
CY7C006 CY7C016
Pin Configurations (continued)
80-Pin TQFP Top View
I/O1L I/O0L SEM L R/W L I/O8L OE L A13L A12L A11L CE L NC A10L VCC A9L A8L A7L 64 NC A6L NC NC 61
80
79
78 77
76
75
74
73
72 71
70
69
68
67
66 65
NC I/O 2L I/O 3L I/O 4L I/O 5L GND I/O 6L I/O 7L V CC NC GND I/O0R I/O1R I/O2R V CC I/O 3R I/O 4R I/O 5R I/O 6R NC
1 2 3 4 5 6 7 8
63 62
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC
9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28
CY7C016
29 30
31
32
33
34
35 36
37
38 39 NC
A 13R
I/O7R
R/WR
SEMR
GND
CER
A9R
A8R
A7R
A6R
NC
NC
NC
40
20
41
I/O8R
OER
A12R
A11R A10R
Pin Definitions
Left Port I/O0L-7L(8L) A0L-13L CEL OEL R/WL SEML Right Port I/O0R-7R(8R) A0R-13R CER OER R/WR SEMR Description Data Bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Interrupt Flag. INTL is set when right port writes location 3FFE and is cleared when left port reads location 3FFE. INTR is set when left port writes location 3FFF and is cleared when right port reads location 3FFF. Busy Flag Master or Slave Select Power Ground
INTL
INTR
BUSYL M/S VCC GND
BUSYR
3
A5R
C006-4
CY7C006 CY7C016
Selection Guide
7C006-15 7C016-15 15 260 70 7C006-25 7C016-25 25 220 60 7C006-35 7C016-35 35 210 50 7C006-55 7C016-55 55 200 40
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current for ISB1 (mA)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage[4]......................................... -0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
7C006-15 7C016-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) Standby Current (One Port CMOS Level) GND VI VCC Outputs Disabled, GND VO V CC VCC = Max., IOUT = 0 mA Outputs Disabled CEL and CER VIH, f = fMAX[5] CEL or CER VIH, f = fMAX[5] Both Ports CE and CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, f = 0[5] One Port CEL or CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, Active Port Outputs, f = fMAX[5] Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind 100 150 3 15 110 170 50 70 -10 -10 170 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 260 -10 -10 160 160 40 40 90 90 3 3 80 80 Min. 2.4 0.4 2.2 0.8 +10 +10 220 270 60 75 130 150 15 15 120 130 mA mA mA mA Typ. Max. 2.4 0.4 7C006-25 7C016-25 Min. Typ. Max. Unit V V V V A A mA
ISB4
Notes: 4. Pulse width < 20 ns. 5. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
4
CY7C006 CY7C016
Electrical Characteristics (continued)
7C006-35 7C016-35 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) Standby Current (One Port CMOS Level) GND VI VCC Outputs Disabled, GND VO V CC VCC = Max., IOUT = 0 mA Com'l Outputs Disabled Ind CEL and CER VIH, f = fMAX[5] CEL or CER VIH, f = fMAX[5] Both Ports CE and CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, f = 0[5] One Port CEL or CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, Active Port Outputs, f = fMAX[5] Com'l Ind Com'l Ind Com'l Ind Com'l Ind -10 -10 150 150 30 30 80 80 3 3 70 70 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 210 250 50 65 120 130 15 15 100 110 -10 -10 140 140 20 20 70 70 3 3 60 60 Min. 2.4 0.4 2.2 0.8 +10 +10 200 240 40 55 100 115 15 15 90 95 mA mA mA mA Typ. Max. 2.4 0.4 7C006-55 7C016-55 Min. Typ. Max. Unit V V V V A A mA
ISB4
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms
5V R1=893 OUTPUT C = 30 pF R2=347 OUTPUT C=30 pF VTH =1.4V (a) Normal Load (Load 1)
C006-5
5V R1=893 OUTPUT C = 5 pF R2=347
RTH =250
(b) Thevenin Equivalent
(Load)
C006-6
(c) Three-State Delay (Load 3)
C006-7
OUTPUT C = 30 pF
3.0V GND 10%
ALL INPUT PULSES 90% 90% 10% 3 ns
C006-9
3 ns Load (Load 2)
C006-8
Note: 6. Tested initially and after any design or process changes that may affect these parameters.
5
CY7C006 CY7C016
Switching Characteristics Over the Operating Range[7]
7C006-15 7C016-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE[8, 9, 10] tHZOE[8, 9, 10] tLZCE[8, 9, 10] tHZCE[8, 9, 10] tPU[10] tPD[10] tWC tSCE tAW tHA tSA tPWE tSD tHD[11] tHZWE[9, 10] tLZWE[9, 10] tWDD[12] tDDD[12] BUSY tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[14] Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down 0 15 3 10 0 25 3 10 3 15 0 35 3 15 10 3 15 3 15 0 55 15 15 3 25 13 3 15 3 25 25 25 3 35 20 3 25 35 35 3 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C006-25 7C016-25 Min. Max. 7C006-35 7C016-35 Min. Max. 7C006-55 7C016-55 Min. Max. Unit
WRITE CYCLE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 3 30 25 15 12 12 0 0 12 10 0 10 3 50 30 25 20 20 0 0 20 15 0 15 3 60 35 35 30 30 0 0 25 15 0 20 3 80 60 55 45 45 0 0 40 25 0 25 ns ns ns ns ns ns ns ns ns ns ns ns
TIMING[13] BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W LOW after BUSY LOW R/W HIGH after BUSY HIGH BUSY HIGH to Data Valid 5 0 13 Note 13 15 15 15 15 5 0 17 Note 13 20 20 20 17 5 0 25 Note 13 20 20 20 25 5 0 30 Note 13 30 30 30 30 ns ns ns ns ns ns ns ns
Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 9. Test conditions used are Load 3. 10. This parameter is guaranteed but not tested. 11. Must be met by the device writing to the RAM under all operating conditions. 12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 13. Test conditions used are Load 2. 14. tBDD is a calculated parameter and is the greater of tWDD - tPWE (actual) or tDDD - tSD (actual).
6
CY7C006 CY7C016
Switching Characteristics Over the Operating Range[7] (continued)
7C006-15 7C016-15 Parameter INTERRUPT tINS tINR tSOP tSWRD tSPS TIMING[13] 15 15 25 25 25 25 30 30 ns ns Description Min. Max. 7C006-25 7C016-25 Min. Max. 7C006-35 7C016-35 Min. Max. 7C006-55 7C016-55 Min. Max. Unit
INT Set Time INT Reset Time
SEMAPHORE TIMING SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window 10 5 5 10 5 5 15 5 5 20 5 5 ns ns ns
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[15, 16]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
C006-10
Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18]
SEM or CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
C006-11
Notes: 15. R/W is HIGH for read cycle. 16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 17. Address valid prior to or coincident with CE transition LOW. 18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
7
CY7C006 CY7C016
Switching Waveforms (continued)
Read Timing with Port-to-Port Delay (M/S=L)[19, 20]
tWC ADDRESSR R/W R MATCH
t PWE
t
SD
t
HD
DATA INR
VALID
ADDRESSL
MATCH tDDD
DATA OUTL tWDD
VALID
C006-12
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23]
tWC ADDRESS tSCE SEM OR CE tAW R/W tSA DATA IN tPWE tSD DATA VALID tHD tHA
OE
t
tHZOE DATA OUT HIGH IMPEDANCE
LZOE
C006-13
Notes: 19. BUSY = HIGH for the writing port. 20. CEL = CER = LOW. 21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 23. R/W must be HIGH during all address transitions.
8
CY7C006 CY7C016
Switching Waveforms (continued)
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[20, 22, 24]
tWC ADDRESS tSCE SEM OR CE tSA R/W tAW tPWE tHA
tSD DATA IN tHZWE DATA OUT DATA VALID
tHD
tLZWE HIGH IMPEDANCE
C006-14
Semaphore Read After Write Timing, Either Side[25]
tAA A0-A 2 VALID ADDRESS tAW SEM tSCE tSD I/O 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE
C006-15
tOHA
VALID ADDRESS tACE tSOP
tHA
DATA IN VALID tPWE tHD
DATA OUT VALID
tDOE
Notes: 24. Data I/O pins enter high-impedance when OE is held LOW during write. 25. CE = HIGH for the duration of the above timing (both write and read cycle).
9
CY7C006 CY7C016
Switching Waveforms (continued)
Semaphore Contention [26, 27, 28]
A0L-A2L MATCH
R/WL SEML tSPS A0R-A 2R MATCH
R/WR SEMR
C006-16
Read with BUSY (M/S=HIGH)[19]
tWC ADDRESSR R/W R MATCH tPWE
tSD DATA IN R tPS ADDRESSL tBLA BUSYL tDDD DATA OUTL tWDD MATCH VALID
tHD
tBHA tBDD
VALID
C006-17
Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
C006-18
Notes: 26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 27. Semaphores are reset (available to both ports) at cycle start. 28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CY7C006 CY7C016
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[29] CELValid First:
ADDRESS L,R CE L tPS CE R tBLC BUSYR
C006-19
ADDRESS MATCH
tBHC
CERValid First:
ADDRESS L,R CE R tPS CE L tBLC BUSYL
C006-20
ADDRESS MATCH
tBHC
Busy Timing Diagram No. 2 (Address Arbitration)[28] Left AddressValid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSYR
C006-21
ADDRESS MISMATCH
tBHA
Right Address Valid First:
tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSYL
C006-22
ADDRESS MISMATCH
tBHA
Notes: 29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. 30. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
11
CY7C006 CY7C016
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR:
tWC ADDRESSL CE L R/WL WRITE 3FFF tHA [30]
INT R tINS[31]
C006-23
Right Side Clears INTR:
ADDRESS R CE R tINR R/WR OE R
tRC READ 3FFF
INTR
C006-24
Right Side Sets INTL:
tWC ADDRESS R CE R WRITE 3FFF tHA [30]
R/W R
INTL tINS [30]
C006-25
Left Side Clears INTL:
ADDRESS R CE L tINR R/W L OEL
tRC READ 3FFF
INT L
C006-26
12
CY7C006 CY7C016
Architecture
The CY7C006/016 consists of a an array of 16K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C006/016 can function as a Master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C006/016 has an automatic power-down feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Interrupts The interrupt flag (INT) permits communications between ports. When the left port writes to location 3FFF(HEX), the right port's interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port's interrupt flag (INTL) is accomplished when the right port writes to location 3FFE(HEX). This flag is cleared when the left port reads location 3FFE(HEX). The message at 3FFE(HEX) and 3FFF(HEX) is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. Busy The CY7C006/016 provides on-chip arbitration to resolve simultaneous memory location access (contention). If both ports' CEs are asserted and an address match occurs within tPS of each other the Busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing of slave devices must be delayed until after the BUSY input has settled (tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C006/016 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request.
Functional Description
Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Table 1. Non-Contending Read/Write Inputs CE H H X H L L L H L X R/W X H X OE X L H X L X X SEM H L X L H H L Outputs I/O 0-7/8 High Z Data Out High Z Data In Data Out Data In Operation Power-Down Read Data in Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition
Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C006/016 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin.
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Set Left INT Reset Left INT Set Right INT Reset Right INT R/W X X L X CE X L L X OE X L X X A0L-13L X 3FFE 3FFF X INT L H X X R/W L X X X CE L L X L Right Port OE X L X L A0R-13R 3FFE X X 3FFF INT X X L H
13
CY7C006 CY7C016
Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O 0 is used. If a 0 is written to the left port of an unused semaphore, a 1 will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a 0) while the left port had control, Table 3. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O 0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All Semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
Ordering Information
16K x8 Dual-Port SRAM Speed (ns) 15 25 Ordering Code CY7C006-15AC CY7C006-15JC CY7C006-25AC CY7C006-25JC CY7C006-25AI CY7C006-25JI CY7C006-35AC CY7C006-35JC CY7C006-35AI CY7C006-35JI CY7C006-55AC CY7C006-55JC CY7C006-55AI CY7C006-55JI Package Name A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 Package Type 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial
35
55
14
CY7C006 CY7C016
Ordering Information (continued)
16K x9 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C016-15AC 25 CY7C016-25AC CY7C016-25AI 35 CY7C016-35AC CY7C016-35AI 55 CY7C016-55AC CY7C016-55AI Document #: 38-00416-B Package Name A80 A80 A80 A80 A80 A80 A80 Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial
80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin
Package Type Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
15
CY7C006 CY7C016
Package Diagrams (continued)
80-Pin Thin Plastic Quad Flat Pack A80
51-85065-B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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